File:FIELD PROGRAMMABLE GATE ARRAY HIGH CAPACITY TECHNOLOGY FOR RADAR AND COUNTER-RADAR DRFM SIGNAL PROCESSING (IA fieldprogrammabl1094559670).pdf

From Wikimedia Commons, the free media repository
Jump to navigation Jump to search
Go to page
next page →
next page →
next page →

Original file(1,275 × 1,650 pixels, file size: 12.04 MB, MIME type: application/pdf, 150 pages)

Captions

Captions

Add a one-line explanation of what this file represents

Summary[edit]

FIELD PROGRAMMABLE GATE ARRAY HIGH CAPACITY TECHNOLOGY FOR RADAR AND COUNTER-RADAR DRFM SIGNAL PROCESSING   (Wikidata search (Cirrus search) Wikidata query (SPARQL)  Create new Wikidata item based on this file)
Author
Grubbs, Hawken L.
Title
FIELD PROGRAMMABLE GATE ARRAY HIGH CAPACITY TECHNOLOGY FOR RADAR AND COUNTER-RADAR DRFM SIGNAL PROCESSING
Publisher
Monterey, CA; Naval Postgraduate School
Description

Radar systems often use low power, continuous waveform radio frequency (RF) modulations and require high-speed adaptive signal processors to provide the necessary processing gain to detect small radar cross-section targets in clutter on range-Doppler maps. Counter-radar technologies include digital RF memories (DRFMs) that attempt to provide multiple, structured false targets with clutter, for example, using a pipelined, finite impulse response arrangement of complex range bin processors. This thesis investigates high-capacity field-programmable gate array (FPGA) technology to enable on-the-fly flexibility and reconfigurability for both radar signal processing and DRFM electronic attack using a Xilinx Virtex Ultrascale+. A three-stage range, Doppler, post-detection integration radar modulation compression circuit is designed and quantified. A range compression circuit with a peak power consumption of 6.100W and a post-implementation utilization of 11% was designed. The Doppler filter bank was designed at 400 MHz with a peak power consumption of 2.688W and a post-implementation utilization of 9%. A coherent integration processor at 400 MHz had a peak power consumption of 2.517W and a post-implementation utilization of 9%. In addition, a DRFM complex range bin processor was designed and quantified at 500 MHz and had a peak power 2.543W with a post-implementation utilization of 11%.


Subjects: LPI radar; low probability of intercept radar; FPGA; field programmable gate array; Virtex Ultrascale+; Vivado; Simulink; DSP; digital signal processing; DRFM; Xilinx
Language English
Publication date June 2018
Current location
IA Collections: navalpostgraduateschoollibrary; fedlink
Accession number
fieldprogrammabl1094559670
Source
Internet Archive identifier: fieldprogrammabl1094559670
https://archive.org/download/fieldprogrammabl1094559670/fieldprogrammabl1094559670.pdf
Permission
(Reusing this file)
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.

Licensing[edit]

Public domain
This work is in the public domain in the United States because it is a work prepared by an officer or employee of the United States Government as part of that person’s official duties under the terms of Title 17, Chapter 1, Section 105 of the US Code. Note: This only applies to original works of the Federal Government and not to the work of any individual U.S. state, territory, commonwealth, county, municipality, or any other subdivision. This template also does not apply to postage stamp designs published by the United States Postal Service since 1978. (See § 313.6(C)(1) of Compendium of U.S. Copyright Office Practices). It also does not apply to certain US coins; see The US Mint Terms of Use.

File history

Click on a date/time to view the file as it appeared at that time.

Date/TimeThumbnailDimensionsUserComment
current12:12, 20 July 2020Thumbnail for version as of 12:12, 20 July 20201,275 × 1,650, 150 pages (12.04 MB) (talk | contribs)FEDLINK - United States Federal Collection fieldprogrammabl1094559670 (User talk:Fæ/IA books#Fork8) (batch 1993-2020 #16411)

Metadata