File:A systematic software, firmware, and hardware codesign methodology for digital signal processing (IA asystematicsoftw1094541358).pdf
Original file (1,275 × 1,650 pixels, file size: 2.62 MB, MIME type: application/pdf, 212 pages)
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Summary[edit]
A systematic software, firmware, and hardware codesign methodology for digital signal processing ( ) | ||
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Author |
Chang, Daniel Y. |
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Title |
A systematic software, firmware, and hardware codesign methodology for digital signal processing |
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Publisher |
Monterey, California: Naval Postgraduate School |
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Description |
Creating an embedded system that meets its functional, performance, cost, and schedule goals is a software-and-hardware codesign problem, since the design of the software and hardware components influence each other. The traditional design methodology is sequential, with hardware designed first and then software. The lack of a unified and unbiased approach can lead to suboptimal design and incompatibilities across the software and hardware boundary. To solve these problems, we propose a new software/firmware/hardware codesign methodology to systematically build correct designs efficiently. This codesign methodology includes requirements development, architecture forming, software/ firmware/hardware partitioning, design-pattern mapping, new-design pattern synthesis, integration, and testing. We tested our methods on three application areas. One was a digitizer-filter architecture for ultra-high frequency signals for which we synthesized design patterns in firmware to meet high-frequency requirements. Another was a digitizer-filter architecture for low-frequency signals. A third was a hidden Markov model using dynamic programming. We implemented and tested the first application on a Tektronix/Synopsys embedded system and the second on a Pentek embedded system based on the requirements provided by the stakeholders Subjects: A*; AND/OR graph; AO*; codesign; concurrent design; data alignment; digital signal processing; design pattern; embedded systems; firmware/software/hardware codesign; FPGA; OR tree; hidden Markov model; polyphase DFT filter banks; post-deserialization bits remapping; pre-serialization bits remapping; switch-and-filter architecture; reconfigurable computing |
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Language | English | |
Publication date | March 2014 | |
Current location |
IA Collections: navalpostgraduateschoollibrary; fedlink |
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Accession number |
asystematicsoftw1094541358 |
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Source | ||
Permission (Reusing this file) |
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted. |
Licensing[edit]
Public domainPublic domainfalsefalse |
This file is a work of a sailor or employee of the U.S. Navy, taken or made as part of that person's official duties. As a work of the U.S. federal government, it is in the public domain in the United States.
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This file has been identified as being free of known restrictions under copyright law, including all related and neighboring rights. |
https://creativecommons.org/publicdomain/mark/1.0/PDMCreative Commons Public Domain Mark 1.0falsefalse
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current | 21:12, 14 July 2020 | 1,275 × 1,650, 212 pages (2.62 MB) | Fæ (talk | contribs) | FEDLINK - United States Federal Collection asystematicsoftw1094541358 (User talk:Fæ/IA books#Fork8) (batch 1993-2020 #8604) |
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Author | Rivera, Janice (CIV) |
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Short title | A systematic software, firmware, and hardware codesign methodology for digital signal processing |
Date and time of digitizing | 02:34, 18 March 2014 |
Software used | Microsoft® Word 2010 |
File change date and time | 10:51, 20 April 2014 |
Date metadata was last modified | 10:51, 20 April 2014 |
Conversion program | Microsoft® Word 2010 |
Encrypted | no |
Page size | 612 x 792 pts (letter) |
Version of PDF format | 1.4 |