Category:Clock and Data Recovery
Clock and Data Recovery is a technique used in the transfer of data from one node of a network to an adjacent one.
The transmission media is generally a structure that guides an electric wave from one end to the other with little attenuation and distortion.
As only a single wave can go through, the data (electric pulses) cannot be transmitted separated from a "container" that allows to distinguish them at the end of the trip.
The container is a periodic signal (= clock) that is mixed with the data before transmission.
The technique to separate clock and data at the reception is a special one that requires special circuits and know-how.
Clock and Data Recovery circuits are generally based on a phase-locked loop.
Therefore this category largely overlaps with "Phase-locked loops", although each retains some specificities of its own.
Media in category "Clock and Data Recovery"
The following 47 files are in this category, out of 47 total.
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2 - 2 and 2 - 1 Application for the De-jitterizer.png 1,169 × 604; 153 KB
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2014 10 28 CDR phase tolerance range vs jitter frequency 2- 2.png 1,788 × 1,259; 285 KB
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2015 12 20 6 Single pole filter for 2-1 CDR.pdf 1,487 × 1,087; 42 KB
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2015 2 14 Jitter transfer bandwidths.pdf 1,770 × 1,010; 45 KB
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2015 3 11 Approx 1 + 2.svg 918 × 241; 190 KB
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2015 3 11 Approx 3 + 4.svg 920 × 233; 191 KB
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2015 3 11 Approx 5 + 6.svg 919 × 224; 192 KB
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2015 3 15 Approx 7 + 8.svg 902 × 189; 186 KB
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2015 3 21 Approx 1 + 2.pdf 1,650 × 447; 84 KB
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2015 3 22 Approx 3 + 4.pdf 1,650 × 443; 126 KB
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2015 3 22 Approx 5 + 6.pdf 1,650 × 420; 115 KB
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2015 3 22 Approx 7 + 8.pdf 1,650 × 435; 120 KB
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2015 3 25 Approx 1 + 2.svg 705 × 177; 180 KB
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2015 3 25 Approx 3 + 4.svg 758 × 167; 237 KB
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2015 3 25 Approx 5 + 6.svg 758 × 149; 226 KB
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2015 3 25 Approx 7 + 8.svg 815 × 170; 229 KB
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2015 4 1 Dejitter via phase al.svg 602 × 439; 217 KB
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2016 1 12 tolerance and modulation index 1 - 1 bbang.png 1,565 × 1,205; 175 KB
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2016 1 12 tolerance and modulation index 2 - 1 linear.png 1,565 × 1,205; 173 KB
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2016 1 12 tolerance and modulation index 2 - 2 bbang.png 1,532 × 1,179; 207 KB
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2016 12 21 Cover page w-o title, w- Planetario Fanzago and description.pdf 1,275 × 1,650; 2.97 MB
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2016 3 5 DeJitterizer with parallel processing.png 673 × 496; 76 KB
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2017 9 20 Fm par to ser n back.pdf 1,752 × 1,239; 43 KB
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2106 3 7 De-jitterizer (full speed clocks).png 1,148 × 524; 126 KB
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An example of elastic buffer.svg 394 × 234; 45 KB
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CDR basic architecture 2.png 531 × 190; 23 KB
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CDR2 2 – 1 - actual shortcomings versus the ideal.png 627 × 439; 60 KB
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Clock paths in the same domain.svg 830 × 380; 112 KB
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Dejitterizing node Djv std.svg 697 × 348; 99 KB
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Elastic buffer operation.png 1,578 × 1,145; 219 KB
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Jitter tol 2-1 with slop. asympt.png 1,530 × 903; 158 KB
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Linear PLLs structures definitions.png 646 × 720; 170 KB
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Lowpass jitter filtering.pdf 1,239 × 1,754; 95 KB
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Non-linear PLLs structures definitions.png 656 × 719; 182 KB
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Ring Oscill DJv pdf IS.svg 563 × 506; 29 KB
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Structures definitions and their fit.pdf 1,500 × 1,125; 56 KB
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Structures.png 1,197 × 721; 237 KB
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The Architecture of the PLL of a CDR is defined by two numbers.pdf 1,500 × 1,125; 40 KB
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Tol & Transf of CDRs in a de-jitterizer.png 673 × 257; 32 KB
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Tol & Transf of CDRs in a de-jitterizer.svg 673 × 257; 34 KB
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Tol vectors at 0.2.png 1,090 × 1,144; 107 KB
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Tol vectors at 0.8.png 1,090 × 1,144; 99 KB
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Tol vectors at 1.0.png 1,090 × 1,144; 96 KB
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Tol vectors at 1.17.png 1,090 × 1,144; 97 KB
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Tol vectors at 2.0.png 1,090 × 1,144; 93 KB
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Tol vectors at 5.0.png 1,100 × 1,144; 88 KB
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USR 2.1 vs zeta.svg 1,456 × 879; 223 KB
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