File:SR (Clocked) Flip-flop Diagram.svg

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Original file(SVG file, nominally 300 × 145 pixels, file size: 22 KB)

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Summary

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Description Gate-level Diagram of a Clocked NAND-gate SR Flip-flop
Date
Source Own Drawing in Inkscape 0.43
Author Inductiveload
Permission
(Reusing this file)
PD

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Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
In some countries this may not be legally possible; if so:
I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

File history

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Date/TimeThumbnailDimensionsUserComment
current09:33, 6 May 2009Thumbnail for version as of 09:33, 6 May 2009300 × 145 (22 KB)Inductiveload (talk | contribs)Clk -> E
01:01, 4 May 2009Thumbnail for version as of 01:01, 4 May 2009300 × 145 (22 KB)Inductiveload (talk | contribs)changed to nor, upgraded symbols
22:36, 17 June 2006Thumbnail for version as of 22:36, 17 June 2006350 × 200 (21 KB)Jjbeard (talk | contribs){{Information |Description=Gate-level Diagram of a Clocked NAND-gate SR Flip-flop |Source=Own Drawing in Inkscape 0.43 |Date=17/06/06 |Author=jjbeard |Permission=PD |other_versions= }} [[

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