File:Häwa jet 64r (Hitachi D-64-S) CPU.jpg
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Summary
[edit]DescriptionHäwa jet 64r (Hitachi D-64-S) CPU.jpg |
English: CPU section of a D-64-S PLC with HD6802 microprocessor, CMOS SRAM and two EEPROMs |
Date | |
Source | Own work |
Author | Phiarc |
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Annotations InfoField | This image is annotated: View the annotations at Commons |
Hitachi HD46802P / HD6802P microprocessor, clone of the Motorola MC6802 with 128 bytes of integrated SRAM
8 kilobyte (8Kx8) EPROM with the PLC firmware
2 kilobyte EPROM with PLC configuration
2 Kilobyte (2Kx8) CMOS SRAM
HD6850P "Asynchronous Communications Interface Adaptor (ACIA)", an UART chip for serial communications. Might be used for communication between PLCs (see "master/slave" switch).
HD14020BP (CD4020 equivalent, likely 5V-compatible) 14-bit counter. Unknown purpose.
Buffers and multiplexers for external I/Os
External interface connector This might be used for connecting multiple PLCs together in conjunction with the "master/slave" switch. It was probably not used for programming, since the configuration is kept in an UV-erased EPROM. It also has way too few pins for direct parallel programming or main bus access.
Optocouplers for digital inputs
Relays for digital outputs
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current | 15:55, 18 February 2023 | ![]() | 8,256 × 5,504 (11.67 MB) | Phiarc (talk | contribs) | Uploaded own work with UploadWizard |
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