Category:Clock gating
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technique used in synchronous circuits for reducing dynamic power dissipation, by adding more logic to a circuit to prune the clock tree (disabling portions of the circuitry so that the flip-flops in them do not have to switch states) | |||||
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Media in category "Clock gating"
The following 4 files are in this category, out of 4 total.
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Clock Gate.png 504 × 308; 9 KB
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Gated clk1.png 812 × 219; 17 KB
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Gated clk2.png 824 × 235; 16 KB
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Gated clk3.png 666 × 257; 47 KB