File:4-fach-NAND-C10.JPG
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[edit]Description4-fach-NAND-C10.JPG |
Deutsch: NAND-Gatter mit 4 Eingängen in Transistor-Transistor-Logik; 7 Transistoren auf dem Chip, kleinste Strukturbreite 20µm (siehe Radio Fernsehen Elektronik 10/1990, S. 649) |
Date | |
Source | Own work |
Author | Dgarte |
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Date/Time | Thumbnail | Dimensions | User | Comment | |
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current | 15:12, 10 April 2012 | 967 × 1,206 (1.6 MB) | Dgarte (talk | contribs) | {{Information |Description=4-faches Nand-Gatter der Transistor-Transistor-Logik |Source={{own}} |Date= 1968 |Author= Dgarte |Permission= |other_versions= }} |
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- Semiconductor device fabrication
- Semiconductor
- Moore's law
- Semiconductor industry
- 90 nm process
- 65 nm process
- International Technology Roadmap for Semiconductors
- ZMDI
- 32 nm process
- Transistor count
- 22 nm process
- 130 nm process
- 180 nm process
- Template:Semiconductor manufacturing processes
- 14 nm process
- 250 nm process
- 800 nm process
- 1 μm process
- 1.5 μm process
- 3 μm process
- 10 µm process
- 600 nm process
- 350 nm process
- Die shrink
- 10 nm process
- 45 nm process
- 5 nm process
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Width | 967 px |
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Height | 1,206 px |
Compression scheme | LZW |
Pixel composition | Palette |
Number of components | 1 |
Number of rows per strip | 12 |
Horizontal resolution | 96 dpi |
Vertical resolution | 96 dpi |