File:Sipeed RV debugger.jpg

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Original file ‎(1,725 × 999 pixels, file size: 313 KB, MIME type: image/jpeg)

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FOSS JTAG+UART debugger based on Bouffalo B702 RISC-V SoC

Summary

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Description
Français : débogueur JTAG+UART libre et à sources ouvertes à (3 €/3,5 US$), basée sur le SoC Bouffalo B702 RISC-V. Le firmware est libre, et la carte, reprogrammable, peut être utilisé pour d'autres types applications. Le microcontrôleur du SoC basé sur un RISC-V RV32 à 144 MHz, comporte un FPU, l'extension cryptographique, et la gestion du WiFi, BlueTooth 5.0 LE, Zigbee 6.0 et ethernet, il gère également l'audio (I2S master/slave), ce qui en fait une machine à tout faire.
English: FOSS (3€/3.5US$) JTAG+UART debugger based on Bouffalo B702 RISC-V SoC. The firmware is free (as FOSS), and the easily reprogrammable board can be used for other kind of applications. The SoC microcontroller is a RISC-V RV32@144Mhz, contain an FPU, crypto extension, manage WiFi, BlueTooth 5.0 LE Zigbee 6.0 and ethernet, audio (I2S master/slave). All this characteristics made this board a general purpose board.
Date
Source Own work
Author Popolon

Licensing

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I, the copyright holder of this work, hereby publish it under the following license:
w:en:Creative Commons
attribution share alike
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Date/TimeThumbnailDimensionsUserComment
current11:26, 19 July 2021Thumbnail for version as of 11:26, 19 July 20211,725 × 999 (313 KB)Popolon (talk | contribs)Uploaded own work with UploadWizard

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