File:INTERCAL Circuitous Diagram.PNG
Original file (744 × 1,010 pixels, file size: 83 KB, MIME type: image/png)
Captions
Captions
![]() |
File:INTERCAL Circuitous Diagram.svg is a vector version of this file. It should be used in place of this PNG file when not inferior.
File:INTERCAL Circuitous Diagram.PNG → File:INTERCAL Circuitous Diagram.svg
For more information, see Help:SVG.
|
Summary
[edit]DescriptionINTERCAL Circuitous Diagram.PNG |
This is a PNG rendering of a picture written in pic from the INTERCAL Programming Language Revised Reference Manual [1], which is licenced under GPL (Copyright (C) 1973 by Donald R. Woods and James M. Lyon, Copyright (C) 1996 by Eric S. Raymond, redistribution encouraged under GPL). Because the picture is licensed under GPL, the source code for the picture (excluding the caption, which was part of the surrounding .mm file) is below. This picture would clearly be better as SVG, but I don't have the software to translate it.
# The CIRCUITOUS DIAGRAM, Figure 1 of the INTERCAL manual. # # Transcribed to PIC by Eric S. Raymond from the paper original. # The transcription is topologically correct but not geometrically perfect. # # I discovered late in the process that the gate spacing to gate width # ratio should be 6/5, not 5/5. The only place the difference shows is # in the zigzag part of the adventitious lead below gate 37, which is # a bit narrower in this version than in the paper original. # # Minor liberties have been taken with the sizes of some features at the # left and right sides to fit the diagram on a letter-sized page. The # A/B input leads should really be a whole boxwidth wide, and the bus line # rectangle was slightly wider and further right in the paper original. # Also, there are only 15 "New York" terminals rather than 16, and in the # original the bus terminal label texts were rotated 90 degrees clockwise. # # The whole diagram can be scaled horizontally or vertically by changing # the boxwid and boxht variables. At default scale the values boxwid = # 0.60 boxht = 0.525 reproduce the paper version most exactly; they get # the gate grid and leads nearly perfect. # scale=6/5 # This is how we scale the whole thing to fit on 8.5x11 boxwid = 0.60 boxht = 0.525 linewid = boxwid lineht = boxht movewid = boxwid moveht = boxht # Offset of top and bottom pins from gate midline define pinoffset {(2/3)} define warmengate { # Draw a Warmenhovian gate box [ box invis; line from last box .sw \ to last box .nw \ to 1/2 <last box .ne, last box .n> \ to 1/2 <last box .e, last box .ne> \ to 1/2 <last box .e, last box .se> \ to 1/2 <last box .se, last box .s> \ to last box .sw; IN: last box .w; UP: pinoffset <last box .w, last box .nw> DN: pinoffset <last box .w, last box .sw> OUT: last box .e; "$1" at last box .center; ] } [ # Beginning of diagram object # Draw the gate array copy thru % move to (($1-1) * movewid * 2, ($2-1) * moveht * 2); warmengate($3) % until "END" 0 1 6 0 2 6 0 3 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 0 10 1 END copy thru % move to ((boxwid + movewid * 7 / 5) + ($1-2) * movewid * 2, ($2-1) * moveht * 2); warmengate($3) % until "END" 1 1 1 1 2 2 1 3 2 1 4 2 1 5 2 1 6 2 1 7 2 1 8 2 1 9 2 1 10 2 2 1 1 2 2 7 2 3 4 2 4 3 2 5 3 2 6 3 2 7 7 2 8 3 2 9 7 2 10 3 3 1 1 3 2 3 3 3 3 3 4 4 3 5 4 3 6 3 3 7 3 3 8 3 3 9 3 3 10 3 4 1 1 4 2 4 4 3 5 4 4 5 4 5 4 4 6 5 4 7 4 4 8 3 4 9 2 4 10 1 END # Draw bus line: BUSLINE: box with .sw at 41st [].se + (boxwid/2, 0) \ wid (boxwid / 2) \ ht (50th [].n.y - 41st [] .s.y) copy thru % move to $1 / 40 <last box .n, last box .s>; "$2" % until "END" 9 B 11 U 13 S 17 L 19 I 21 N 23 E 30 8 END define newyork { line right boxwid/3 box invis "" "TO" "NEW" "YORK" "" } define philly { line right boxwid/3 box invis "" "TO" "PHILA-" "DELPHIA" "" } for i = 0 to 14 do { move to (i+1)/18 <BUSLINE.ne,BUSLINE.se> newyork } move to (i+1)/18 <BUSLINE.ne,BUSLINE.se> philly define dot {circle rad 0.03 filled 1} # Place a junction dot wherever we are define junction % {dot at Here}; % # Draw inputs define inwidth {boxwid*3/4} define drawinputs { line left inwidth from $1.UP; "A" at last line .end - (0.1, 0) rjust; "$2" at last line .end - (0.05, 0.1) rjust; move to last line .center; A$2: junction line left inwidth from $1.DN; "B" at last line .end - (0.1, 0) rjust; "$2" at last line .end - (0.05, 0.1) rjust; move to last line .center; B$2: junction } drawinputs(3rd [],8) drawinputs(4th [],7) drawinputs(5th [],6) drawinputs(6th [],5) drawinputs(7th [],4) drawinputs(8th [],3) drawinputs(9rd [],2) # Gate 10 inputs have to be done by hand define go {move to $1;} # Define `gate' to *refer* to nth gate define gate {`$1'th []} # Go to specified pin of given gate define pin {gate($1).$2} # We exploit the quantization of lead placements here # Draw from left edge of box $1 quanta of inter-box horizontal distance define left_mv {line left boxwid * $1 / 5;} # Draw from right edge of box $1 quanta of inter-box horizontal distance define right_mv {line right boxwid * $1 / 5;} # Draw from top pin of box $1 quanta of inter-box vertical distance up define up_mv {line up (boxht * (2 - pinoffset)) * $1 / 4;} # Draw from bottom pin of box $1 quanta of inter-box vertical distance down define dn_mv {line down (boxht * (2 - pinoffset)) * $1 / 4;} # Draw from here to given object, with directional constraint define vert {line up ($1.y - Here.y);} define horz {line right ($1.x - Here.x);} define zig {vert($1) horz($1)} define to_bus {line to (BUSLINE.w, Here)} define ground { dn_mv(1) [ boxwid = boxwid * (3/4) boxht = boxht / 3 box invis line from last box .ne to last box .nw line from 1/3 <last box.e,last box.c> to 1/3 <last box.w,last box.c> line from 2/3 <last box.se,last box.s> to 2/3 <last box.sw,last box.s> ] } # Now all those connections # Gate 1: go(pin(1,OUT)) right_mv(3) CORNER:Here; zig(pin(12,DN)) go(CORNER) vert(pin(1,UP)) \ {junction horz(pin(11,UP))} \ up_mv(2) junction horz(gate(32).e) right_mv(3) junction {zig(pin(43,IN))} horz(gate(42).e) right_mv(1) junction {to_bus} vert(pin(43,UP)) up_mv(2) to_bus # Gate 2 go(pin(2,OUT)) right_mv(2) zig(pin(12,UP)) # Gate 3 go(A8) up_mv(1) horz(gate(13).e) right_mv(3) zig(pin(23,IN)) go(B8) dn_mv(1) horz(gate(13)) right_mv(1) dn_mv(1) horz(gate(23).e) right_mv(2) dn_mv(2) horz(pin(32,UP)) go(pin(3,OUT)) right_mv(2) vert(gate(3).UP) up_mv(3) horz(gate(13).e) right_mv(2) vert(gate(15,UP)) up_mv(4) #??? don't know why 4 is necessary horz(gate(16).w) left_mv(1) vert(gate(6).w) up_mv(4) left_mv(2) zig(pin(7,OUT)) # Gate 4 go(A7) up_mv(1) horz(gate(14).e) right_mv(1) zig(pin(24,UP)) go(B7) dn_mv(1) horz(gate(4)) right_mv(1) dn_mv(1) horz(gate(14).e) right_mv(3) vert(pin(26,UP)) up_mv(1) horz(gate(25)) up_mv(2) horz(gate(25).e) right_mv(4) vert(pin(38,UP)) up_mv(1) horz(gate(48).e) right_mv(1) vert(pin(47,DN)) dn_mv(1) horz(gate(47).w) left_mv(3) vert(gate(46).DN) dn_mv(2) right_mv(2) vert(gate(45).DN) dn_mv(2) left_mv(3) vert(gate(44).DN) right_mv(3) dn_mv(2) horz(gate(33).w) left_mv(1) vert(gate(33).DN) dn_mv(3) horz(gate(32).e) up_mv(2) horz(gate(42).e) dn_mv(2) line down boxwid/5 to_bus go(pin(4,OUT)) right_mv(3) junction {zig(pin(13,UP))} vert(pin(4,UP)) up_mv(3) junction {right_mv(3) zig(pin(15,IN))} left_mv(2) vert(pin(7,UP)) up_mv(3) right_mv(3) zig(pin(19,DN)) # Gate 5 go(A6) up_mv(1) horz(gate(15).e) right_mv(1) vert(pin(15,UP)) junction {horz(pin(25,UP))} vert(pin(15,DN)) dn_mv(1) horz(gate(25).e) right_mv(1) zig(pin(34,UP)) go(B6) dn_mv(2) horz(gate(25).e) dn_mv(1) right_mv(4) vert(pin(24,DN)) dn_mv(1) horz(gate(34).e) right_mv(1) vert(pin(32,DN)) dn_mv(1) right_mv(3) zig(pin(42,IN)) go(pin(5,OUT)) right_mv(5) junction {vert(pin(14,IN)) junction {horz(pin(14,IN))} zig(pin(13,IN)) } vert(pin(17,DN)) junction {horz(pin(17,DN))} zig(pin(18,DN)) # Gate 6 go(A5) up_mv(1) horz(gate(16).e) right_mv(1) zig(pin(26,UP)) go(B5) dn_mv(2) horz(gate(26).e) right_mv(3) zig(pin(34,IN)) go(pin(6,OUT)) right_mv(4) junction {horz(pin(16,IN))} vert(pin(15,DN)) junction {horz(pin(15,DN))} vert(pin(14,DN)) junction {horz(pin(14,DN))} zig(pin(13,DN)) # Gate 7 go(A4) up_mv(1) horz(gate(27).e) right_mv(3) vert(pin(37,IN)) junction {horz(pin(37,IN))} vert(pin(37,DN)) dn_mv(2) right_mv(1) junction {zig(pin(36,IN))} horz(gate(37).e) right_mv(3) zig(pin(45,IN)) go(B4) dn_mv(2) horz(gate(17).e) right_mv(4) vert(pin(26,DN)) dn_mv(1) horz(gate(26).e) dn_mv(2) right_mv(4) vert(pin(35,DN)) dn_mv(1) horz(gate(35).e) right_mv(2) junction {zig(pin(45,UP))} {zig(pin(44,UP))} # Gate 8 go(A3) up_mv(1) horz(gate(28).e) right_mv(1) zig(pin(38,UP)) go(B3) dn_mv(2) horz(gate(28).e) right_mv(2) zig(pin(37,UP)) go(pin(8,OUT)) right_mv(6) junction {zig(pin(17,IN))} up_mv(4) left_mv(1) vert(pin(19,UP)) junction {horz(pin(19,UP))} zig(pin(20,UP)) # Gate 9 go(A2) up_mv(1) horz(gate(19).e) right_mv(1) zig(pin(28,UP)) go(B2) dn_mv(2) horz(gate(39).e) right_mv(1) vert(pin(38,DN)) dn_mv(2) right_mv(2) zig(pin(47,IN)) go(pin(9,OUT)) right_mv(3) junction {zig(pin(20,DN))} {horz(pin(19,IN))} vert(pin(16,DN)) junction {horz(pin(16,DN))} zig(pin(15,UP)) # Gate 10 line left inwidth from 10th[].UP; "A" at last line .end - (0.1, 0) rjust; "1" at last line .end - (0.05, 0.1) rjust; move to last line .center; A1: junction line left inwidth from 10th [].DN; "B" at last line .end - (0.1, 0) rjust; "1" at last line .end - (0.05, 0.1) rjust; move to 1/2 <last line .center, last line .start>; B1: junction go(A1) vert(pin(10,DN)) dn_mv(1) horz(gate(20).e) right_mv(2) zig(pin(30,UP)) go(B1) dn_mv(2) horz(gate(30).e) right_mv(1) junction {zig(pin(39,UP))} right_mv(3) zig(pin(40,DN)) go(pin(10,OUT)) right_mv(2) junction {horz(pin(20,IN))} vert(pin(18,UP)) junction {horz(pin(18,UP))} vert(pin(16,UP)) junction {horz(pin(16,UP))} zig(pin(14,UP)) # Gate 11 go(pin(11, DN)) left_mv(3) vert(pin(11,UP)) up_mv(1) \ horz(gate(31).e) right_mv(1) zig(pin(41,DN)) go(pin(11,OUT)) right_mv(2) zig(pin(21,DN)) # Gate 12 go(pin(12,OUT)) right_mv(3) junction {horz(pin(22,IN))} vert(pin(12,UP)) up_mv(1) horz(gate(12).w) left_mv(3) zig(pin(12,IN)) # Gate 13 go(pin(13,OUT)) right_mv(1) zig(pin(23,UP)) # Gate 14 go(pin(14,OUT)) horz(pin(24,IN)) # Gate 15 go(pin(15,OUT)) horz(pin(25,IN)) # Gate 16 go(pin(16,OUT)) right_mv(2) junction {horz(pin(26,IN))} vert(pin(27,UP)) junction {horz(pin(27,UP))} zig(pin(29,DN)) # Gate 17 go(pin(17,OUT)) horz(pin(27,IN)) # Gate 18 go(pin(18,OUT)) right_mv(3) junction {horz(pin(28,IN))} zig(pin(27,DN)) # Gate 19 go(pin(19,OUT)) horz(pin(29,IN)) # Gate 20 go(pin(20,OUT)) right_mv(3) junction {horz(pin(30,IN))} zig(pin(29,UP)) # Gate 21 go(pin(21,UP)) left_mv(2) vert(pin(21,DN)) ground go(pin(21,OUT)) right_mv(2) junction {zig(pin(31,DN))} up_mv(2) junction # Gate 22 go(pin(22,UP)) left_mv(3) up_mv(2) junction go(pin(22,DN)) left_mv(4) vert(pin(22,UP)) up_mv(3) right_mv(3) vert(pin(23,UP)) up_mv(3) horz(gate(23).e) right_mv(2) vert(pin(25,UP)) left_mv(1) vert(pin(28,DN)) right_mv(1) zig(pin(40,IN)) go(pin(22,OUT)) right_mv(3) junction {horz(pin(32,IN))} {zig(pin(33,IN))} zig(pin(31,UP)) # Gate 23 go(pin(23,OUT)) right_mv(1) vert(gate(23).DN) dn_mv(1) horz(gate(33)) right_mv(1) dn_mv(1) to_bus # Gate 24 go(pin(24,OUT)) right_mv(1) zig(pin(33,UP)) # Gate 25 go(pin(25,OUT)) horz(pin(35,IN)) # Gate 26 go(pin(26,OUT)) right_mv(2) vert(pin(26,DN)) dn_mv(1) junction {to_bus} zig(pin(35,UP)) # Gate 27 go(pin(27,OUT)) right_mv(2) zig(pin(36,UP)) # Gate 28 go(pin(28,OUT)) right_mv(3) junction {horz(pin(38,IN))} vert(pin(38, DN)) dn_mv(1) to_bus # Gate 29 go(pin(29,OUT)) right_mv(3) junction {horz(pin(39,IN))} {vert(pin(39, DN)) dn_mv(1) to_bus} zig(pin(40,UP)) # Gate 30 go(pin(30,OUT)) right_mv(1) vert(pin(30,DN)) dn_mv(1) horz(gate(40).e) right_mv(2) zig(pin(50,UP)) # Gate 31 go(pin(31,OUT)) right_mv(2) zig(pin(41,UP)) # Gate 32 go(pin(32,OUT)) right_mv(2) vert(pin(32,UP)) junction {horz(pin(42,UP))} up_mv(1) to_bus # Gate 33 go(pin(33,OUT)) right_mv(2) zig(pin(43,UP)) # Gate 34 go(pin(34,OUT)) right_mv(3) junction {horz(pin(44,IN))} vert(pin(44, DN)) dn_mv(1) to_bus # Gate 35 go(pin(35,OUT)) right_mv(1) dn_mv(1) right_mv(2) dn_mv(1) to_bus # Gate 36 go(pin(36,OUT)) horz(pin(46,IN)) # Gate 37 go(pin(37,OUT)) right_mv(2) vert(pin(48,UP)) junction {horz(pin(48,UP))} zig(pin(49,DN)) # Gate 38 go(pin(38,OUT)) right_mv(3) junction {horz(pin(48,IN))} vert(pin(48,DN)) right_mv(1) dn_mv(3) left_mv(3) vert(pin(47,UP)) junction {horz(pin(47,UP))} zig(pin(46,UP)) # Gate 39 go(pin(39,OUT)) right_mv(3) junction {horz(pin(49,IN))} {vert(pin(49, DN)) dn_mv(2) to_bus} zig(pin(50,IN)) # Gate 40 go(pin(40,OUT)) right_mv(1) vert(pin(40,DN)) dn_mv(2) junction {horz(gate(40).w); dn_mv(1); horz(gate(40).e); right_mv(1)} dn_mv(1) junction zig(pin(49,UP)) # Gate 41 # (should be right_mv(2) but we've squeezed the bus line a bit left) go(pin(41,OUT)) right_mv(1) vert(pin(41,DN)) ground # Gate 42 go(pin(42,OUT)) to_bus # Gate 43 go(pin(43,OUT)) to_bus # Gate 44 go(pin(44,OUT)) to_bus # Gate 45 go(pin(45,OUT)) to_bus # Gate 46 go(pin(46,OUT)) to_bus # Gate 47 go(pin(47,OUT)) to_bus # Gate 48 go(pin(48,OUT)) to_bus # Gate 49 go(pin(49,OUT)) to_bus # Gate 50 go(pin(50,OUT)) to_bus # The adventitious lead go(pin(17,OUT)) right_mv(1) {vert(pin(17,UP)) up_mv(3) horz(gate(17))} vert(pin(17,DN)) dn_mv(1) horz(gate(27).w) dn_mv(1) horz(gate(27).e) dn_mv(1) horz(gate(36).w) up_mv(2) right_mv(1) dn_mv(2) right_mv(1) up_mv(2) right_mv(1) dn_mv(2) right_mv(1) up_mv(2) right_mv(1) vert(pin(37,DN)) right_mv(4) dn_mv(2) right_mv(3) dn_mv(1) left_mv(3) vert(pin(46,DN)) left_mv(3) dn_mv(3) horz(gate(36).w) up_mv(1) horz(gate(36)) right_mv(1) ] # End of diagram object |
||
Date | Original (on paper) created in 1972 or 1973, converted to PIC (by Eric S. Raymond) in 1996, converted to PNG 11 October 2006, uploaded to en:Wikipedia 11 October 2006, to Commons 24 October 2006. | ||
Source | INTERCAL Programming Language Revised Reference Manual [2] | ||
Author | User Ais523 on en.wikipedia | ||
Permission (Reusing this file) |
|
||
Other versions |
Originally from en.wikipedia; description page is (was) here * 09:02, 11 October 2006 [[:en:User:Ais523|Ais523]] 744×1010 (85,021 bytes) <span class="comment">({{GPL}} This is a PNG rendering of a picture written in pic from the INTERCAL Programming Language Revised Reference Manual [http://www.catb.org/~esr/intercal/intercal.ps.gz], which is licenced under GPL (Copyright (C) 1973 by Donald R. Woods and James M.)</span> |
(Uploaded using CommonsHelper or PushForCommons)
File history
Click on a date/time to view the file as it appeared at that time.
Date/Time | Thumbnail | Dimensions | User | Comment | |
---|---|---|---|---|---|
current | 11:20, 24 October 2006 | 744 × 1,010 (83 KB) | Ais523 (talk | contribs) | {{Information| |Description= This is a PNG rendering of a picture written in pic from the INTERCAL Programming Language Revised Reference Manual [http://www.catb.org/~esr/intercal/intercal.ps.gz], which is licenced under GPL (Copyright (C) 1973 by Donald |
You cannot overwrite this file.
File usage on Commons
There are no pages that use this file.