File:Diagramme logique CMOS 4006 TI.png
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Français : Diagramme logique du circuit CMOS 4006 (d'après Texas Instruments). Chacun des quatre registres à décalage est constitué d'une chaîne de bascules D. Le premier et le troisième registre à décalage comptent quatre étages ; le second et le quatrième en comptent cinq. Seule la sortie du quatrième étage des registres, et celle du cinquième quand il existe, est accessible. Le premier registre à décalage dispose d'une sortie latchée, sauf chez certains constructeurs (la sortie correspondante du circuit est alors non connectée). Toutes les bascules sont commandées par une unique entrée d'horloge CLOCK. Les fronts descendants du signal changent l'état de sortie des bascules D des registres ; ses fronts montants changent l'état de sortie du latch. |
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| Source | Own work |
| Author | PA5CAL France |
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| current | 19:34, 14 May 2022 | | 900 × 960 (42 KB) | PA5CAL France (talk | contribs) | Uploaded own work with UploadWizard |
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