File:Computer Systems - Von Neumann Architecture Large poster anchor chart.svg

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English: Following research on posters and their cognitive load effect, I’m at a stage where my classroom has very few displays. As a rule, any posters that I have up need to be readable from anywhere in the room and big enough for me to physically illustrate the processes, so this will be 136cm x 81cm in size. Made up from 20x A3 sheets. As this is an vector file (SVG), you will be able to scale this to any size.

I felt that none of the diagrams in textbooks/slides/online quite cover the GCSE Computer Science specification and lead to misconceptions.

In an ideal world, I wouldn’t include CIR and I would include a multi-core processor so I could show how L3 Cache is shared across the cores. The CIR is necessary as I’d like my A-Level Computer Science students to commit the diagram to memory. L3 Cache/multi core was omitted as it would over-complicate the diagram perhaps.

Level: (14 years+)

Teaches: (CPU, memory hierarchy, Virtual memory, systems architecture)
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Author William Lau
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I, the copyright holder of this work, hereby publish it under the following license:
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Date/TimeThumbnailDimensionsUserComment
current20:40, 8 December 2018Thumbnail for version as of 20:40, 8 December 20181,191 × 842 (349 KB)Mrlaulearning (talk | contribs)User created page with UploadWizard

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