File:CMOS OR.svg

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Original file (SVG file, nominally 375 × 250 pixels, file size: 4 KB)

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Description Layout of NMOS and PMOS components in an OR Gate. This OR gate is implemented as an AND gate with both inputs inverted(by using PMOS at the top) as well as the output (inverter at the right) which is functionally correct, but is not commonly used as it requires 2 extra transistors.
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Source Own work using: Inkscape 0.43
Author inductiveload
SVG development
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Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
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Date/TimeThumbnailDimensionsUserComment
current18:24, 21 January 2020Thumbnail for version as of 18:24, 21 January 2020375 × 250 (4 KB)GKFX (talk | contribs)Use <text> rather than text as path to give better thumbnails
19:25, 24 March 2014Thumbnail for version as of 19:25, 24 March 2014375 × 250 (21 KB)Wereldburger758 (talk | contribs)Valid SVG now.
19:40, 12 July 2006Thumbnail for version as of 19:40, 12 July 2006375 × 250 (29 KB)Inductiveload (talk | contribs){{Information |Description=Layout of NMOS and PMOS components in an OR Gate |Source=Own drawing, Inkscape 0.43 |Date=12/07/06 |Author=inductiveload |Permission=PD |other_versions= }} Category:CMOS

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