File:3 bit shif tregister.jpg
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3_bit_shif_tregister.jpg (454 × 164 pixels, file size: 8 KB, MIME type: image/jpeg)
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[edit]Description3 bit shif tregister.jpg |
English: A three-bit serial-in serial-out (SISO) shift register. This circuit introduces a 3-cycle delay in the data line. |
Date | |
Source | Lecturer's notes |
Author | Dr. Ray Eaton |
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[edit]Public domainPublic domainfalsefalse |
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Date/Time | Thumbnail | Dimensions | User | Comment | |
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current | 13:31, 23 April 2008 | ![]() | 454 × 164 (8 KB) | JFonseka (talk | contribs) | {{Information |Description=Common circuit diagram |Source=Lecturer's notes |Date=23/04/2008 |Author=Dr. Ray Eaton |Permission=Fair use |other_versions= }} |
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23 April 2008
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42ee7e095cbf5e7e83004d2a89b2fcc6747113b6
8,206 byte
164 pixel
454 pixel
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